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RT8856 1 ds8856-03 june 2011 www.richtek.com multi-phase pwm controller for cpu core power supply features z z z z z 1/2 phase pwm controller with 2 integrated mosfet drivers z z z z z imvp6.5 compatible power management states (dpsrlvr, psi, extended deeper sleep mode) z z z z z navp (native avp) topology z z z z z 7-bit dac z z z z z 0.8% dac accuracy z z z z z fixed v boot (1.1v) z z z z z differential remote voltage sensing z z z z z programmable output transition slew rate control z z z z z accurate current and thermal balance z z z z z system thermal compensation avp z z z z z ringing free mode at light load conditions z z z z z fast transient response z z z z z power good z z z z z clock enable output z z z z z thermal throttling z z z z z current monitor output z z z z z switching frequency up to 1mhz per phase z z z z z ovp, uvp, nvp, ocp, otp, uvlo z z z z z 40-lead wqfn package z z z z z rohs compliant and halogen free general description the RT8856 is a single/dual phase pwm controller with two integrated mosfet drivers. moreover, it is compliant with intel imvp6.5 voltage regulator specification to fulfill its mobile cpu vcore power supply requirements. the RT8856 adopts navp tm (native avp) which is richtek's proprietary topology derived from finite dc gain compensator peak current mode, making it an easy setting pwm controller that meets all intel avp (active voltage positioning) mobile cpu requirements. the output voltage of the RT8856 is set by 7-bit vid code. the built-in high accuracy dac converts the vid code ranging from 0v to 1.5v with 12.5mv per step. the system accuracy of the controller can reach 1.5%. the part supports vid on-the-fly and mode change on-the-fly functions that are fully compliant with imvp6.5 specification. it operates in single phase, dual phase and rfm. it can reach up to 90% efficiency in different modes according to different loading conditions. the droop load line can be easily programmed by setting the dc gain of the error amplifier. with proper compensation, the load transient can achieve optimized avp performance. this chip controls soft-start and output transition slew rate via a capacitor. it supports both dcr and sense resistor current sensing. the current mode navp tm topology with high accuracy current sensing amplifier well balances the RT8856's channel currents. the RT8856 provides power good, clock enabling and thermal throttling output signals for imvp6.5 specification. it also features complete fault protection functions including over voltage, under voltage, negative voltage, over current, thermal shutdown, and under voltage lockout. the RT8856 is available in a wqfn-40l 6x6 small foot print package. applications z imvp6.5 core supply z multi-phase cpu core supply z avp step-down converter z notebook/ desktop computer/ servers ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. marking information RT8856 gqw ymdnn RT8856gqw : product number ymdnn : date code package type qw : wqfn-40l 6x6 (w-type) RT8856 lead plating system g : green (halogen free and pb free)
RT8856 2 ds8856-03 june 2011 www.richtek.com typical application circuit pin configurations (top view) wqfn-40l 6x6 30 29 28 27 26 25 24 23 22 21 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 ugate2 phase2 pgnd2 lgate2 pvcc lgate1 pgnd1 phase1 ugate1 boot1 dprslpvr vron fs cm vid6 vid5 vid4 vid3 vid2 vid1 vid0 comp fb vsen rgnd soft isen1 isen1_n gnd p s i c m s e t 41 p g o o d v c c t o n n t c o c s e t i s e n 2 i s e n 2 _ n b o o t 2 v r t t c l k e n v o u t v i d 0 v i d 1 v i d 2 v i d 3 v i d 4 5 v 1 0 2 2 2 3 2 5 7 8 9 6 2 4 2 0 3 1 1 1 3 2 3 0 2 9 2 7 2 8 1 6 3 9 4 0 3 6 3 3 1 5 v i d 0 v i d 1 v i d 2 v i d 3 u g a t e 1 u g a t e 2 i s e n 1 _ n r t 8 8 5 6 v i d 4 v i d 5 d p r s l p v r b o o t 2 l g a t e 1 p g n d 1 i s e n 2 v r o n n t c p h a s e 2 i s e n 2 _ n g n d p g n d 2 s o f t v i d 5 1 2 1 1 p v c c 2 1 2 6 c o m p v c c r g n d b o o t 1 p g o o d v i d 6 1 4 3 8 3 5 3 2 1 8 1 7 3 4 v i d 6 p h a s e 1 l g a t e 2 v s e n f b o c s e t i s e n 1 1 9 r 8 r 7 r 1 1 d p r s l p v r v r o n p w r g d 3 . 3 v r 2 3 r 2 2 v c c l 1 v i n c 8 l 2 v i n c 2 r 6 c 6 r 1 4 c 1 0 c 1 7 r 2 6 r 2 9 v c c c 1 1 r 1 9 c p u v s s s e n s e c 3 c 1 4 c 1 5 c 1 c 9 r 1 c 4 q 1 q 2 q 3 q 4 r 2 r 3 r 4 7 v t o 2 4 v r 5 c 5 d 1 r 9 r 1 0 r 1 2 7 v t o 2 1 v r 1 3 c 9 d 2 r 2 7 r 2 8 n t c 2 v c c p c m 4 c m c 1 2 r 1 5 r 2 1 n t c 1 f s 3 r 2 5 c 1 8 r 2 4 c p u v c c s e n s e r 2 0 v o u t c l k e n c l k e n v r t t v r t t p s i p s i 4 1 ( e x p o s e d p a d ) c 7 v i n 3 7 t o n r 1 6 r 1 7 c 1 3 c 1 6 c p u v s s s e n s e 5 c m s e t r 1 8
RT8856 3 ds8856-03 june 2011 www.richtek.com table 1. imvp6.5 vid code table vid6 vid5 vid4 vid3 vid2 vid1 vid0 output 0 0 0 0 0 0 0 1.5000v 0 0 0 0 0 0 1 1.4875v 0 0 0 0 0 1 0 1.4750v 0 0 0 0 0 1 1 1.4625v 0 0 0 0 1 0 0 1.4500v 0 0 0 0 1 0 1 1.4375v 0 0 0 0 1 1 0 1.4250v 0 0 0 0 1 1 1 1.4125v 0 0 0 1 0 0 0 1.4000v 0 0 0 1 0 0 1 1.3875v 0 0 0 1 0 1 0 1.3750v 0 0 0 1 0 1 1 1.3625v 0 0 0 1 1 0 0 1.3500v 0 0 0 1 1 0 1 1.3375v 0 0 0 1 1 1 0 1.3250v 0 0 0 1 1 1 1 1.3125v 0 0 1 0 0 0 0 1.3000v 0 0 1 0 0 0 1 1.2875v 0 0 1 0 0 1 0 1.2750v 0 0 1 0 0 1 1 1.2625v 0 0 1 0 1 0 0 1.2500v 0 0 1 0 1 0 1 1.2375v 0 0 1 0 1 1 0 1.2250v 0 0 1 0 1 1 1 1.2125v 0 0 1 1 0 0 0 1.2000v 0 0 1 1 0 0 1 1.1875v 0 0 1 1 0 1 0 1.1750v 0 0 1 1 0 1 1 1.1625v 0 0 1 1 1 0 0 1.1500v 0 0 1 1 1 0 1 1.1375v 0 0 1 1 1 1 0 1.1250v 0 0 1 1 1 1 1 1.1125v 0 1 0 0 0 0 0 1.1000v vid6 vid5 vid4 vid3 vid2 vid1 vid0 output 0 1 0 0 0 0 1 1.0875v 0 1 0 0 0 1 0 1.0750v 0 1 0 0 0 1 1 1.0625v 0 1 0 0 1 0 0 1.0500v 0 1 0 0 1 0 1 1.0375v 0 1 0 0 1 1 0 1.0250v 0 1 0 0 1 1 1 1.0125v 0 1 0 1 0 0 0 1.0000v 0 1 0 1 0 0 1 0.9875v 0 1 0 1 0 1 0 0.9750v 0 1 0 1 0 1 1 0.9625v 0 1 0 1 1 0 0 0.9500v 0 1 0 1 1 0 1 0.9375v 0 1 0 1 1 1 0 0.9250v 0 1 0 1 1 1 1 0.9125v 0 1 1 0 0 0 0 0.9000v 0 1 1 0 0 0 1 0.8875v 0 1 1 0 0 1 0 0.8750v 0 1 1 0 0 1 1 0.8625v 0 1 1 0 1 0 0 0.8500v 0 1 1 0 1 0 1 0.8375v 0 1 1 0 1 1 0 0.8250v 0 1 1 0 1 1 1 0.8125v 0 1 1 1 0 0 0 0.8000v 0 1 1 1 0 0 1 0.7875v 0 1 1 1 0 1 0 0.7750v 0 1 1 1 0 1 1 0.7625v 0 1 1 1 1 0 0 0.7500v 0 1 1 1 1 0 1 0.7375v 0 1 1 1 1 1 0 0.7250v 0 1 1 1 1 1 1 0.7125v 1 0 0 0 0 0 0 0.7000v 1 0 0 0 0 0 1 0.6875v to be continued
RT8856 4 ds8856-03 june 2011 www.richtek.com vid6 vid5 vid4 vid3 vid2 vid1 vid0 output 1 0 0 0 0 1 0 0.6750v 1 0 0 0 0 1 1 0.6625v 1 0 0 0 1 0 0 0.6500v 1 0 0 0 1 0 1 0.6375v 1 0 0 0 1 1 0 0.6250v 1 0 0 0 1 1 1 0.6125v 1 0 0 1 0 0 0 0.6000v 1 0 0 1 0 0 1 0.5875v 1 0 0 1 0 1 0 0.5750v 1 0 0 1 0 1 1 0.5625v 1 0 0 1 1 0 0 0.5500v 1 0 0 1 1 0 1 0.5375v 1 0 0 1 1 1 0 0.5250v 1 0 0 1 1 1 1 0.5125v 1 0 1 0 0 0 0 0.5000v 1 0 1 0 0 0 1 0.4875v 1 0 1 0 0 1 0 0.4750v 1 0 1 0 0 1 1 0.4625v 1 0 1 0 1 0 0 0.4500v 1 0 1 0 1 0 1 0.4375v 1 0 1 0 1 1 0 0.4250v 1 0 1 0 1 1 1 0.4125v 1 0 1 1 0 0 0 0.4000v 1 0 1 1 0 0 1 0.3875v 1 0 1 1 0 1 0 0.3750v 1 0 1 1 0 1 1 0.3625v 1 0 1 1 1 0 0 0.3500v 1 0 1 1 1 0 1 0.3375v 1 0 1 1 1 1 0 0.3250v 1 0 1 1 1 1 1 0.3125v 1 1 0 0 0 0 0 0.3000v vid6 vid5 vid4 vid3 vid2 vid1 vid0 output 1 1 0 0 0 0 1 0.2875v 1 1 0 0 0 1 0 0.2750v 1 1 0 0 0 1 1 0.2625v 1 1 0 0 1 0 0 0.2500v 1 1 0 0 1 0 1 0.2375v 1 1 0 0 1 1 0 0.2250v 1 1 0 0 1 1 1 0.2125v 1 1 0 1 0 0 0 0.2000v 1 1 0 1 0 0 1 0.1875v 1 1 0 1 0 1 0 0.1750v 1 1 0 1 0 1 1 0.1625v 1 1 0 1 1 0 0 0.1500v 1 1 0 1 1 0 1 0.1375v 1 1 0 1 1 1 0 0.1250v 1 1 0 1 1 1 1 0.1125v 1 1 1 0 0 0 0 0.1000v 1 1 1 0 0 0 1 0.0875v 1 1 1 0 0 1 0 0.0750v 1 1 1 0 0 1 1 0.0625v 1 1 1 0 1 0 0 0.0500v 1 1 1 0 1 0 1 0.0375v 1 1 1 0 1 1 0 0.0250v 1 1 1 0 1 1 1 0.0125v 1 1 1 1 0 0 0 0.0000v 1 1 1 1 0 0 1 0.0000v 1 1 1 1 0 1 0 0.0000v 1 1 1 1 0 1 1 0.0000v 1 1 1 1 1 0 0 0.0000v 1 1 1 1 1 0 1 0.0000v 1 1 1 1 1 1 0 0.0000v 1 1 1 1 1 1 1 0.0000v
RT8856 5 ds8856-03 june 2011 www.richtek.com functional pin description pin no. pin name pin function 1 dprslpvr deeper sleep mode signal. together with psi, the combination of these two pins indicates the power management states. 2 vron voltage regulator enabler. 3 fs frequency setting. connect this pin with a resistor to ground to set the operating frequency. 4 cm current monitor output. this pin outputs a voltage proportional to the output current. 5 cmset current monitor output gain externally setting. connect this pin with one resistor to vsen while cm pin is connected to ground with another resistor. the current monitor output gain can be set by the ratio of these two resistors. 6 to 12 vid[6:0] voltage id. dac voltage identification inputs for imvp6.5. the logic threshold is 30% of vccp as the maximum value for low state and 70% of vccp as the minimum value for the high state. vccp is 1.05v. 13 psi power status indicator ii. together with dprslpvr, the combination of these two pins indicates the power management states. 14 comp compensation. this pin is the output node of the error amplifier. 15 fb feedback. this is the negative input node of the error amplifier. 16 vsen positive voltage sensing pin. this pin is the positive node of the differential voltage sensing. 17 rgnd return ground. this pin is the negative node of the differential remote voltage sensing. 18 soft soft-start. this pin provides soft-start function and slew rate control. the capacitance of the slew rate control capacitor is restr icted to be larger than 10nf. the feedback voltage of the converter follows the ramping voltage on the soft pin during soft-start and other voltage transitions according to different modes of operation and vid change. 19 isen1 positive input of phase1 current sense. 20 isen1_n negative input of phase1 current sense. 21 boot1 bootstrap power pin of phase1. this pin powers the high side mosfet drivers. connect this pin to the junction of the bootstrap capacitor with the cathode of the bootstrap diode. connect the anode of the bootstrap diode to the pvcc pin. 22 ugate1 upper gate drive of phase1. this pin drives the gate of the high side mosfets. 23 phase1 return node of phase1 high side driver. connect this pin to high side mosfet sources together with the low side mosfet drains and the inductor. 24 pgnd1 driver ground of phase1. 25 lgate1 lower gate drive of phase1. this pin drives the gate of the low side mosfets. 26 pvcc driver power. 27 lgate2 lower gate drive of phase2. this pin drives the gate of the low side mosfets. 28 pgnd2 driver ground of phase2. 29 phase2 return node of phase2 high side driver. connect this pin to high side mosfet sources together with the low side mosfet drains and the inductor. to be continued
RT8856 6 ds8856-03 june 2011 www.richtek.com pin no. pin name pin function 30 ugate2 upper gate drive of phase2. this pin drives the gate of the high side mosfets. 31 boot2 bootstrap power pin of phase2. this pin powers the high side mosfet drivers. connect this pin to the junction of the bootstrap capacitor with the cathode of the bootstrap diode. connect the anode of the bootstrap diode to the pvcc pin. 32 isen2_n negative input of phase2 current sense. 33 isen2 positive input of phase2 current sense. 34 ocset over current protection setting. connect a resistive voltage divider from vcc to ground and connect the joint of the voltage divider to the ocset pin. the voltage, v ocset , determines the over current threshold, i lim . 35 ntc thermal detection input for vrtt circuit. connect this pin with a resistive voltage divider from vcc using ntc on the top to set the thermal management threshol d level. 36 vrtt voltage regulator thermal throttling. this open-drain output pin indicates the temperature exceeding the preset level when it is pulled low. 37 ton connect this pin to vin with one resistor. this resistor value sets the ripple size in ringing free mode. 38 vcc chip power. 39 clken inverted clock enable. this open-drain pin is an output indicating the start of the pll locking of the clock chip. 40 pgood power good indicator. 41 (exposed pad) gnd ground. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation.
RT8856 7 ds8856-03 june 2011 www.richtek.com function block diagram comp rgnd soft ovp trip point vid1 vid3 vid4 vid5 vid0 vid2 fb pgood vcc gnd error amp ocp setting osc soft start nvp trip point fs power on reset & central logic vsen vron ocset ntc vid6 mode selection dprslpvr 1.2v uvp trip point otp + - vcc mux dac + - + - + - + - + - + - isen1_n pwmcp pwmcp driver logic control pgnd2 lgate2 phase2 ugate2 boot2 pgnd1 lgate1 pvcc phase1 ugate1 boot1 isen1 isen2_n isen2 cm one_phase - + - + 1/2 + - 20 + - 20 + c l k e n v r t t p s i cm cmset ringing free mode ton fb offset cancellation
RT8856 8 ds8856-03 june 2011 www.richtek.com electrical characteristics parameter symbol test conditions min typ max unit supply input supply current i vcc + i pvcc r fs = 33k , v vron = 3.3v, not switching -- -- 10 ma shutdown current i cc + i pvcc v vron = 0v -- -- 5 a soft-start/slew rate control (based on 10nf c ss ) soft-start / soft-shutdown i ss1 v soft = 1.5v 16 20 24 a deeper sleep exit/vid change slew current i ss2 v soft = 1.5v 80 100 120 a recommended operating conditions (note 4) z supply voltage, v cc ------------------------------------------------------------------------------------ 4.5v to 5.5v z battery voltage, v in ------------------------------------------------------------------------------------- 7v to 24v z junction temperature range -------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range -------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) z vcc to gnd ---------------------------------------------------------------------------------------------- ? 0.3v to 6.5v z rgnd, pgndx to gnd --------------------------------------------------------------------------------- ? 0.3v to 0.3v z vidx to gnd ---------------------------------------------------------------------------------------------- ? 0.3v to (v cc + 0.3v) z psi, vron to gnd -------------------------------------------------------------------------------------- ? 0.3v to (v cc + 0.3v) z pgood, clken, vrtt to gnd --------------------------------------------------------------------- ? 0.3v to (v cc + 0.3v) z vsen, fb, comp, soft, fs, ocset, cm, cmset, ntc to gnd -------------------------- ? 0.3v to (v cc + 0.3v) z isenx, isen1_n, isen2_n to gnd ---------------------------------------------------------------- ? 0.3v to (v cc + 0.3v) z pvcc to pgndx ---------------------------------------------------------------------------------------- ? 0.3v to 6.5v z lgatex to pgndx -------------------------------------------------------------------------------------- ? 0.3v to (pvcc + 0.3v) z phasex to pgndx ------------------------------------------------------------------------------------- ? 3v to 28v z bootx to phasex ------------------------------------------------------------------------------------- ? 0.3v to 6.5v z ugatex to phasex ------------------------------------------------------------------------------------ ? 0.3v to (bootx ? phasex) z pgood ---------------------------------------------------------------------------------------------------- ? 0.3v to (v cc + 0.3v) z power dissipation, p d @ t a = 25 c wqfn ? 40l 6x6 ------------------------------------------------------------------------------------------ 2.941w z package thermal resistance (note 2) wqfn-40l 6x6, ja ------------------------------------------------------------------------------------- 34 c/w wqfn-40l 6x6, jc ------------------------------------------------------------------------------------- 6 c/w z junction temperature ----------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) ------------------------------------------------------------- 260 c z storage temperature range --------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ----------------------------------------------------------------------------- 2kv mm (machine mode) ------------------------------------------------------------------------------------ 200v (v cc = 5v, t a = 25 c, unless otherwise specified) to be continued
RT8856 9 ds8856-03 june 2011 www.richtek.com to be continued parameter symbol test conditions min typ max unit oscillator frequency f osc r fs = 33k , v dac > 1.05 270 300 330 khz frequency varia tio n r fs = 5k to 50k ? 20 -- 20 % frequency range per phase 200 -- 1000 khz maximum duty c ycle per phase -- 50 -- % fs pin output voltage v fs r fs = 33k , v dac > 1.05 1 1.05 1.1 v reference and dac v dac = 0.7500 ? 1.5000 (no load, active mode ) ? 0.8 0 0.8 %vid dc accuracy v fb v dac = 0.5000 ? 0.7500 ? 7.5 0 7.5 mv boot voltage v boot 1.089 1.1 1.111 v error amplifier dc gain r l = 47k 70 80 -- db gain-bandwidth product gbw c load = 5pf -- 10 -- mhz slew rate sr c load = 10pf (gain = ? 4, r f = 47k , v out = 0.5v ? 3v) -- 5 -- v/ s output voltage range v comp r l = 47k 0.5 -- 3.6 v max source/sink current i outea v comp = 2v -- 250 -- a current sense amplifier input offset voltage v oscs ? 1 -- 1 mv impedance at neg. input r is enx_n 1 -- -- m impedance at pos. input r is enx 1 -- -- m dc gain a i -- 10 -- v/v input range v isenx_in ? 50 -- 100 mv rfm ton setting ton pin output voltage v ton r ton = 8 0k , v ton = v dac = 0.75v ? 5 0 5 % dem on-time setting t on i rton = 8 0 a -- 350 -- ns r ton current range i rto n 25 -- 280 a protection under voltage lockout threshold v uvlo falling edge 4.1 4.3 4.5 v under voltage lockout threshold hysteresis v uvlo -- 200 -- mv absolute over voltage protection threshold v ovabs (with respect to 1.5v, 50mv) 1.45 1.5 1.55 v relative over voltage protection threshold v ov (with respect to v vid , 50mv) 150 200 250 mv under voltage protection threshold v uv measured at vsen with respect to unloaded output voltage (uov) (for 0.8 < uov < 1.5) ? 350 ? 300 ? 250 mv negative voltage protection threshold v nv measured at vsen with respect to gnd ? 100 -- -- mv
RT8856 10 ds8856-03 june 2011 www.richtek.com parameter symbol test conditions min typ max unit current limit threshold voltage (average) v ilim (v isenx ? v is enx_n ) / n, v ocset = 0.625v, v ilimt(nom) = 25mv 23 25 27 mv current limit threshold voltage (per phase) v ilim_ph v ilimitph / v ilimit -- 150 -- % thermal shutdown threshold t sd -- 160 -- c thermal shutdown hyster esis t sd -- 10 -- c logic inputs logic-high v ih with respect to 3.3v, 70% 2.31 -- -- vron input threshold voltage logic-low v il with respect to 3.3v, 30% -- -- 0.99 v leakage current of vron ? 1 -- 1 a logic-high v ih with respect to 1.1v, 70% 0.77 -- -- dac (vid0 ? vid6), psi and dprslpvr input threshold voltage logic-low v il with respect to 1.1v, 30% -- -- 0.33 v leakage current of dac (vid0 ? vid6), psi and dprslpvr ? 1 -- 1 a power good pgood threshold v th_pgood -- 1 -- v pgood low voltage v pgood i pgood = 4ma -- -- 0.4 v pgood delay t pgood clken low to pgood high 3 -- 20 ms clock enable clken low voltage v clken i clken = 4ma -- -- 0.4 v thermal throttling thermal throttling threshold v ot measure at ntc with respect to v cc -- 80 -- %v dd thermal throttling threshold hysteresis v ot _hy at v cc = 5v -- 100 -- mv vrtt output voltage v vrtt i vrtt = 40ma -- -- 0.4 v current monitor current monitor maximum output voltage in operating range v dac = 1v, v rcmset = 90mv, r cm = 50k , r cmset = 1 0k 0.855 0.9 0.945 v current monitor maximum output voltage -- -- 1.15 v gate driver ugate driver source r ugatesr v bootx ? v phasex = 5v v bootx ? v ugatex = 1v -- 0.7 -- ugate driver sink r ugatesk v ugate = 1v -- 0.6 -- l gat e dri ve r source r lgatesr v pvcc = 5v, v pvcc ? v lgate = 1v -- 0.7 -- l gat e dri ve r sink r lgatesk v lgate = 1v -- 0.3 -- ugate driver source/sink current i ugate v boot ? v phase = 5v v ugate = 2.5v -- 3 -- a lgate driver source current i lgatesr v lgate = 2.5v -- 3 -- a to be continued
RT8856 11 ds8856-03 june 2011 www.richtek.com note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in natural convection at t a = 25 c on a high effective thermal conductivity four-layer test board of jedec 51-7 thermal measurement standard. the measured case position of jc is on the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol test conditions min typ max unit l gat e dri ve r sink current i lg atesk v lg ate = 2.5v -- 5 -- a internal boost charging switch on-resistance r boot pvcc to bootx -- 30 --
RT8856 12 ds8856-03 june 2011 www.richtek.com typical operating characteristics ccm vcc_sense vs. load current 1.04 1.06 1.08 1.1 1.12 1.14 1.16 0 1020304050 load current (a) vcc_sense (v) ccm efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0 1020304050 load current (a) efficiency (%) v in = 8v v in = 12v v in = 19v vid = 0.9375v, r fs = 33 k , dprslpvr = gnd, psi = high ccm efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0 1020304050 load current (a) efficiency (%) v in = 8v v in = 12v v in = 19v vid = 1.15v, r fs = 33 k , dprslpvr = gnd, psi = high dem efficiency vs. load current 50 55 60 65 70 75 80 85 90 95 00.511.522.53 load current (a) efficiency (%) v in = 8v v in = 12v v in = 19v vid = 0.85v, r fs = 33 k , dprslpvr = gnd, psi = high v in = 8v v in = 12v v in = 19v vid = 1.15v, r fs = 33 k , dprslpvr = gnd, psi = high ccm vcc_sense vs. load current 0.84 0.86 0.88 0.90 0.92 0.94 0.96 0 1020304050 load current (a) vcc_sense (v) v in = 8v v in = 12v v in = 19v vid = 0.9375v, r fs = 33 k , dprslpvr = gnd, psi = high v cm vs. load current 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 0 1020304050 load current (a) v cm (mv) v in = 8v v in = 12v v in = 19v vid = 0.9375v, r fs = 33 k , dprslpvr = gnd, psi = high
RT8856 13 ds8856-03 june 2011 www.richtek.com ccm vid change up time (20 s/div) v cc sense (100mv/div) vid0 (2v/div) v in = 12v, vid change from 0.85v to 0.9375v lgate1 (1v/div) ugate1 (20v/div) dprslpvr = gnd, psi = high, no load power off from vron time (1ms/div) v cc sense (500mv/div) vron (5v/div) v in = 12v, vid = 0.9375v pgood (1v/div) ugate (2v/div) dprslpvr = gnd, psi = high, no load rfm vid cha nge down time (40 s/div) v cc sense (100mv/div) lgate1 (5v/div) v in = 12v, vid change 0.9375v to 0.85v, ugate1 (20v/div) vid0 (2v/div) dprslpvr = high, no load ccm vid cha nge down time (20 s/div) v cc sense (100mv/div) vid0 (2v/div) v in = 12v, vid change from 0.9375v to 0.85v lgate1 (5v/div) ugate1 (20v/div) dprslpvr = gnd, psi = high, no load ccm load transient response time (4 s/div) v cc sense (50mv/div) lgate1 (5v/div) v in = 12v, vid = 0.95v, i load = 12a to 51a, dprslpvr = gnd, psi = high ugate1 (20v/div) power on from vron time (1ms/div) v cc sense (500mv/div) vron (5v/div) v in = 12v, vid = 0.9375v pgood (1v/div) ugate (20v/div) dprslpvr = gnd, psi = high, no load
RT8856 14 ds8856-03 june 2011 www.richtek.com over current protection time (10 s/div) v cc sense (500mv/div) lgate1 (10v/div) v in = 12v, vid = 0.9375v, dprslpvr = gnd i load (50a/div) pgood (1v/div) under voltage protection time (10 s/div) v cc sense (1v/div) lgate1 (5v/div) v in = 12v, vid = 0.9375v, dprslpvr = gnd ugate1 (20v/div) pgood (2v/div) over voltage protection time (10 s/div) v cc sense (1v/div) lgate1 (5v/div) v in = 12v, vid = 0.9375v, dprslpvr = gnd ugate1 (20v/div) pgood (2v/div) dprslpvr = gnd, psi = high ccm load transient response time (4 s/div) v cc sense (50mv/div) lgate1 (5v/div) v in = 12v, vid = 0.95v, i load = 51a to 12a, ugate1 (20v/div)
RT8856 15 ds8856-03 june 2011 www.richtek.com application information the RT8856 is a 1/2-phase dc/dc controller and includes embedded gate drivers for reduced system cost and board area. the number of phases is not only user selectable, but also dynamically changeable based on intel's imvp6.5 control signals to optimize efficiency. phase currents are continuously sensed for loop control, droop tuning, and over current protection. the internal 7-bit vid dac and a low offset differential amplifier allow the controller to maintain high voltage regulating accuracy to meet intel's imvp6.5 specification. design tool to reduce the efforts and errors caused by manual calculations, a user friendly design tool is now available on request. this design tool calculates all necessary design parameters by entering user ' s requirements. please contact richtek ' s representatives for details. phase selection and operation modes the maximum number of operating phase is programmable by setting isen2_n. after the initial turn-on of the RT8856, an internal comparator checks the voltage at the isen2_n pin. to set the RT8856 as a pure single phase pwm controller, connect isen2_n to a voltage higher than (v cc - 1v) at power on. the controller will then disable phase 2 (hold ugate2 and lgate2 low) and operate as a single phase pwm controller. the RT8856 also works in conjunction with intel's iimvp6.5 control signals, such as psi and dprslpvr. table 2 shows the control signal truth table for operation modes of the RT8856. for high current demand, the controller will operate with both phases active. these two phase gate signals are interleaved. this achieves minimal output voltage ripple and best transient performance. for reduced current demand, only one phase is active. for 1-phase operation, the power stage can minimize switching losses and maintain transient response capability. at lowest current levels, the controller enters single phase ringing-free mode (rfm) to achieve highest efficiency. table 2. control signal truth table for operation modes dprslpvr psi ope rat ion mode 0 1 multi-phase ccm 0 0 single-phase ccm 1 1 s single-phase rfm, slow c4e 1 0 single-phase rfm, slow c4e differential remote sense setting the RT8856 includes differential, remote sense inputs to eliminate the effects of voltage drops along the pc board traces, cpu internal power routes and socket contacts. the cpu contains on-die sense pin voltages, v cc_sense and v ss_sense . v ss_sense is connected to rgnd pin. the v cc_sense is connected to fb pin with a resistor to build the negative input path of the error amplifier. connect vsen to v cc_sense for clken, pgood, ovp, and uvp sense. the 7-bit vid dac and the precision voltage reference are referred to rgnd for accurate remote sensing. current sense setting the RT8856 continuously sense the output current of each phase. therefore, the controller can be less noise sensitive and get more accurate current sharing between phases. low offset amplifiers are used for loop control and current limit. the internal current sense amplifier gain (a i ) is fixed to be 10. the isenx and isenx_n denote the positive and negative input of the current sense amplifier of each phase, respectively. users can either use a current-sense resistor or the inductor's dcr for current sensing. using inductor's dcr allows higher efficiency as shown in figure 1. if x x l rc dcr = (1) then the current sense performance will be optimum. for example, choosing l = 0.36 h with 1m dcr and c x = 100nf, yields r x : == ? x 0.36 h r3.6k 1.0m 100nf (2)
RT8856 16 ds8856-03 june 2011 www.richtek.com similar to the peak current mode control with finite compensator gain, the hs_fet on-time is determined by both the internal clock and the pwm comparator which compares the ea output with the output of current sense amplifier. when load current increases, v cs increases, the steady state comp voltage also increases and makes the v out decrease, hence achieving avp. a near-dc offset (v ofs ) is added to the output ea to cancel the inherent output offset of finite-gain peak current mode controller. in rfm, hs_fet is turned on with constant ton when v cs is lower than v comp2 . once the hs_fet is turned off, ls_fet is turned on automatically. by ringing-free technique, the ls_fet allows only partial of negative current when the inductor free-wheeling current reaches negative. the switching frequency will be proportionately reduced, thus the conduction and switching losses will be greatly reduced. droop setting (with temperature compensation) it's very easy to achieve active voltage positioning (avp) by properly setting the error amplifier gain with respect to the native droop characteristics. the target is to have equation (3) v out = v soft ? i load x r droop (3) figure 1. lossless inductor sensing since the inductance tolerances are normally observed to be 20%, the resistor, r x , has to be tuned on board by examining the transient voltage. if the output voltage transient has an initial dip below the minimum load line requirement with a slow recovery, r x is chosen too small. vice versa, with a resistance too large, the output voltage transient has only a small initial dip and the recovery is too fast, thus causing a ring-back. using current sense resistor in series with the inductor can have better accuracy, but the efficiency is a trade-off. considering the equivalent inductance (l esl ) of the current sense resistor, an rc filter is recommended. the rc filter calculation method is similar to the above-mentioned inductor dcr sensing method . loop control the RT8856 adopts richtek's proprietary navp tm topology. navp tm is based on the finite-gain peak current mode pwm topology. the output voltage, v out , will decrease with increasing output load current. the control loop consists of pwm modulator with power stage, current sense amplifier and error amplifier as shown in figure 2. figure 2. simplified schematic for droop and remote sense in ccm then solving the switching condition v comp2 = v cs in figure 2 yields the desired error amplifier gain as isense v droop ar r2 a r1 r == (4) w here a i is the internal current sense amplifier gain. r sense is the current sense resistor. if there is no external sense resistor, it is the dcr of the inductor. r droop is the resistive slope value of the converter output and is the desired static output impedance, e.g. ? 1.9m or ? 3m for imvp6.5 specification. increasing a v can make load line more shallow as shown in figure 3. a v1 a v2 a v2 > a v1 v out load current 0 figure 3. error amplifier gain (a v ) influence on v out accuracy phasex isenx isenx_n v out l dcr r x c x + v x - c bypass v out v cc_sense pwm logic ugatex lgatex + - isenx isenx_n a i - + r s clock cmp v cs comp2 - + v ss_sense v in fb soft rgnd comp RT8856 hs_fet ls_fet l r x c x r c c c2 c1 r2 r1 c soft v ofs ea + - v dac
RT8856 17 ds8856-03 june 2011 www.richtek.com since the dcr of induc tor is highly temperature dependent, it affects the output accuracy at hot co nditions. temperature compensation is recommended for the lossless inductor dcr current sense method. figure 4 shows a simple but effective way of compensating the temperature variations of the sense resistor using an ntc thermistor placed in the feedback path. figure 4. loop setting with temperature compensation usually, r1a is set to equal r ntc (25 c). r1b is selected to linearize the ntc's temperature characteristic. for a given ntc, design is to get r1b and r2 and then c1 and c2. according to equation (4), to compensate the temperature variations of the sense resistor, the error amplifier gain (a v ) should have the same temperature coefficient with r sense . hence, v, hot sense, hot v, cold sense, cold ar ar = (5) from equation (4), av can be obtained at any temperature (t) as shown below : v, t ntc, t r2 a r1a // r r1b = + (6) the standard formula for the resistance of ntc thermistor as a function of temperature compensation is given by : ( ) ( ) { } 11 t+273 298 ntc, t 25 rr e ?? ? ?? ?? = (7) where r 25 is the thermistor's nominal resistance at room temperature, (beta) is the thermistor's material constant in kelvins, and t is the thermistor's actual temperature in celsius. to calculate dcr value at different temperature, use the equation below : dcr t = dcr 25 x [1 + 0.00393 x (t ? 25)] (8) where the 0.00393 is the temperature coefficient of the copper. for a given ntc thermistor, solving equation (6) at room temperature (25 c) yields r2 = a v, 2 5 x (r1b + r1a // r ntc, 25 ) (9) where a v, 2 5 is the error amplifier gain at room temperature and can be obtained from equation (4). r1b can be obtained by substituting equation (9) to (5), sense, hot ntc, hot ntc, hot sense, cold sense, hot sense, cold r1b r (r1a // r ) (r1a // r ) r r 1 r = ? ?? ? ?? ?? (10) loop compensation optimized compensation of the RT8856 allows for best possible load step response of the regulator's output. a type-ii compensator with one pole and one zero is adequate for a proper compensation. figure 4 shows the compensation circuit. prior design procedure shows how to select the resistive feedback components for the error amplifier gain. next, the c1 and c2 must be calculated for the compensation. the target is to achieve constant resistive output impedance over the widest possible frequency range. the pole frequency of the compensator must be set to compensate the output capacitor esr zero : p c 1 f 2cr = (11) where c is the capacitance of output capacitor, and r c is the esr of output capacitor. c2 can be calculated as follows : c cr c2 r2 = (12) the zero of compensator has to be placed at half of the switching frequency to filter the switching related noise. such that, (13) () ntc, 25 sw 1 c1 r1b r1a // r f = + v cc_sense - + v ss_sense fb soft rgnd comp RT8856 c2 c1 r2 r1b c soft 10nf ea r1a ntc + - v dac
RT8856 18 ds8856-03 june 2011 www.richtek.com frequency setting high frequency operation optimizes the application for smaller component size, but trads off efficiency due to higher switching losses. this may be acceptable in ultra- portable devices where the load currents are lower and the controller is powered from a lower voltage supply. low frequency operation offers the best overall efficiency at the expense of component size and board space. connect a resistor (r fs ) between fs and ground to set the switching frequency (f sw ) per phase : (14) fs sw 300(khz) 33(k ) r(k) f(khz) = a resistor of 5k to 50k corresponds to switching frequency of 1mhz to 200khz, respectively. soft-start and mode change slew rates the RT8856 uses 2 slew rates for various modes of operation. these two slew rates are internally determined by commanding one of two bi-directional current sources on to the soft pin (i ss ). the 7-bit vid dac and the precision voltage reference are referred to rgnd for accurate remote sensing. hence, connect a capacitor (c soft ) from soft pin to rgnd for controlling the slew rate as shown in figure 4. the capacitance of capacitor is restricted to be larger than 10nf. the voltage on soft pin (v soft ) is higher than the reference voltage of the error amplifier at about 0.9v. the first current of typically 20 a is used to charge or discharge the c soft during soft-start, soft-shutdown. the second current of typically 100 a is used during other voltage transitions, including vid change and transitions between operation modes. the imvp6.5 specification specifies the critical timing associated with regulating the output voltage. the symbol, slewrate, as given in the imvp6.5 specification will determine the choice of the soft capacitor, c soft, by the following equation : (15) = ss soft i(a) c(nf) slewrate(mv / s) power up sequence with the controller's vcc voltage above the por threshold (typ. 4.3v), the power-up sequence begins when vron exceeds the 3.3v logic high threshold. approximately 20 s later, soft and v core starts ramping up to boot voltage (1.1v) with maximum phases. the slew rate during power-up is 20 a/c soft . the RT8856 pulls clken low after v vsen rises above 1v for 73 s. right after clken goes low, soft and v core starts ramping to first dac value. after clken goes low for approximate 4.7ms, pgood is asserted high. dprslpvr and psi are valid right after pgood is asserted. uvp is masked as long as v soft is less than 1v. figure 5. timing diagram for power-up and power-down power down when vron goes low, the RT8856 enters low-power shutdown mode. pgood is pulled low immediately and v soft ramps down with slew rate of 20 a/c soft . v vsen also ramps down following v soft with maximum phases. after v vsen falls below 200mv, the RT8856 turns off both high side and low side mosfets. a discharging resistor at vsen will be enabled and the analog part will be turned off. deeper sleep mode transitions after dprslpvr goes high, the RT8856 immediately disables phase 2 (ugate2 and lgate2 forced low) and enters 1-phase deeper sleep mode operation. if the vids are set to a lower voltage setting, the output drops at a rate determined by the load and the output capacitance. the internal target v soft still ramps as before, and uvp, ocp and ovp are masked for 73 s. vron vcc 4.3v 4.1v vid valid x x xx v core pgood 73s typ. 4.7ms typ. por 0.2v 1.1v 1v valid xx xx valid xx xx pwm max phases pull low max phases hi-z dprslpvr/psi defined psi clken dprslpvr
RT8856 19 ds8856-03 june 2011 www.richtek.com the RT8856 provides 2 slew rates for deeper sleep mode entry/ exit. for standard deeper sleep exit, the RT8856 immediately activates all enabled phases and ramps the output voltage to the dac code provided by the processor at the slew rate of 100 a/c soft . the RT8856 remains in 1-phase ringing free mode and ramps the output voltage to the dac code provided by the processor at the slew rate of 20 a/c soft . current limit setting the RT8856 compares a programmable current limit set point to the voltage from the current sense amplifier output for over current protection (ocp). the voltage applied to ocset pin defines the desired current limit threshold, i lim : v ocset = 25 x i lim x r sense (16) connect a resistive voltage divider from vcc to gnd, with the joint of the voltage divider connected to ocset pin as shown in figure 6. for a given r oc2 , (17) cc oc1 oc2 ocset v rr 1 v ?? = ? ?? ?? v cc ocset RT8856 r oc1 r oc2 figure 6. ocp setting without temperature compensation the ocp works in two stages : ` stage 1 : average inductor current exceeds the current limit threshold, i lim , defined by v ocset , but remains smaller than 150% of i lim if the over current condition remains valid for 16 cycles, the ocp latches and the system shuts down. ` stage 2 : any inductor current exceeds 150% of i lim then ocp latches instantaneously. latched ocp forces driver high impedance with ugatex = 0 and lgatex = 0. after latched ocp happens, v vsen will be monitored. when v vsen falls below 200mv, a discharging resistor at vsen will be enabled. if inductor dcr is used as current sense component, then temperature compensation is recommended to protect under all conditions. figure 7 shows a typical ocp setting with temperature compensation. figure 7. ocp setting with temperature compensation v cc ocset RT8856 r oc1b r oc2 r oc1a ntc usually, select r oc1a equal to thermistor's nominal resistance at room temperature. ideally, v ocset should have same temperature coefficient as r sense (inductor dcr) : ocset, hot sense, hot ocset, cold sense, cold vr vr = (18) according to the basic circuit calculation, v ocset can be obtained at any temperature : oc2 ocset, t oc1a ntc, t oc1b oc2 r v r//r r r = ++ (19) re-w rite equation ( 18) from (19), and get v ocset at room temperature oc1a ntc, cold oc1b oc2 sense, hot oc1a ntc, hot oc1b oc2 sense, cold r//r r r r r//r r r r ++ = ++ (20) (21) oc2 ocset, 25 oc1a ntc, 25 oc1b oc2 r v r//r r r = ++ so lving equation (20 ) and (21) yields r oc1b and r oc2 (22) oc2 equ, hot equ, cold equ, 25 cc ocset, 25 r rr (1)r v (1 ) v = ? + ? ? (23) oc1b oc2 equ, hot equ, cold r (1)r r r (1 ) = ? + ? ? where sense, hot 25 hot sense, cold 25 cold r dcr [1 0.00393 (t 25)] r dcr [1 0.00393 (t 25)] = + ? = + ? (24)
RT8856 20 ds8856-03 june 2011 www.richtek.com r equ, t = r1a // r ntc, t (25) for example, the following design parameters are given : dcr =1m , v cc = 5v, i l, ripple = 5a r oc1a = r ntc, 25 = 10k , ntc = 2400 for ? 20 c to 100 c operation range, to set ocp trip current i trip = 57a when operating with maximum phases : lim ocset, 25 57a i 5a 33.5a 2 v 25 33.5a 1m 0.8375v =+= = = r ntc, ? 20 =41.89k , r ntc, 100 = 1.98k r sense, ? 20 =0.82 m , r sense, 100 =1.29m r oc2 = 2.437k , r oc1b = 7.113k over voltage protection (ovp) the ovp circuit is triggered under two conditions : ` condition 1 : when v vsen exceeds 1.55v. ` condition 2 : when v vsen exceeds v dac by 200mv. if either condition is valid, the RT8856 latches the lgatex =1 and ugatex = 0 as crowbar to the output voltage of vr. turning on all ls_fets can lead to very large reverse inductor current and potentially result in negative output voltage of vr. to prevent damage of the cpu by negative voltage, the RT8856 turns off all ls_fets when v vsen has fallen below ? 100mv. under voltage protection (uvp) if v vsen is less than v dac by 300mv or more, a uvp fault is latched and the RT8856 turns off both upper side and lower side mosfets. v vsen is monitored after uvp is valid. when v vsen falls below 200mv, a discharging resistor at vsen will be enabled. negative voltage protection (nvp) during shutdown or protection state, when v vsen is lower than ? 100mv, the controller will force lgatex = 0 and ugatex = 0 for preventing negative voltage. once v vsen recovers to be more than 0mv, nvp will be suspended and lgatex = 1 will be enabled again. over temperature protection (otp) over temperature protection prevents the vr from damage. otp is considered to be the final protection stage against overheating of the vr. the thermal throttling vrtt should be set to assert prior to otp to manage the vr power. when this measure is insufficient to keep the die temperature of the controller below the otp threshold, otp will be asserted and latched. the die temperature of the controller is monitored internally by a temperature sensor. as a result of otp triggering, a soft shutdown will be launched and v vsen will be monitored. when v vsen is less than 200mv, the driver remains in high impedance state and the discharging resistor at vsen pin will be enabled. a reset can be executed by cycling vcc or vron. thermal throttling control intel imvp6.5 technology supports thermal throttling of the processor to prevent catastrophic thermal damage. the RT8856 includes a thermal monitoring circuit to detect an exceeded user defined temperature on a vr point. the thermal monitoring circuit senses the voltage change across the ntc pin. figure 8 shows the principle of setting the temperature threshold. connect an external resistive voltage divider between vcc and gnd. this divider uses a negative temperature coefficient (ntc) thermistor and a resistor. the joint of the voltage divider is connected to the ntc pin in order to generate a voltage that is proportional to the temperature. the RT8856 pulls vrtt low if the voltage on the ntc pin is greater than 0.8 x v cc . the internal vrtt comparator has a hysteresis of 100mv to prevent high frequency vrtt oscillation when the temperature is near the setting point. the minimum assertion/de-assertion time for vrtt toggling is 1.5ms. ? v cc ntc RT8856 + - 0.8 x v cc r oc1b r oc2 v r t t cmp figure 8. thermal throttling setting principle
RT8856 21 ds8856-03 june 2011 www.richtek.com users can use the same ntc thermistor for both thermal throttling and current limit setting as shown in figure 9. just divide the r oc1b into r tta and r ttb , and write the v ntc equation at thermal throttling temperature tt c : r tta + r ttb = r oc1b (26) oc2 ttb cc oc2 oc1b oc1a ntc, tt c cc rr v rr r//r 0.8 v + ++ = (27) solving (26) and (27) for r tta and r ttb as : r ttb = 4 x (r oc1a // r ntc, tt c ) ? r oc2 (28) r tta = r oc1b ? r ttb (29) ntc RT8856 + - 0.8 x v cc v r t t cmp v cc r oc1b r oc2 r oc1a ntc figure 9. using single ntc thermistor for thermal throttling and current limit setting current monitor the current monitor allows the system to accurately monitor the cpu's current dissipation and quickly predict whether the system is about to overheat before the significantly slower temperature sensor signals an over temperature alert. the voltage output of cm pin is proportional to the output current. this pin is connected to ground with one resistor while cmset pin is connected to v vsen with another resistor. by choosing the appropriate ratio of these two resistors, current monitor gain can be set and v cm will be 1v with maximum output current. maximum value of v cm is clamped at 1.15v. = cm cm load droop cmset r vi r 2 r (30) inductor selection the switching frequency and ripple current determine the inductor value as follows : out(min) min min sw ripple v(1d) ln fi ? = (31) where n is the total number of phases. d min is the minimum duty at highest input voltage v in . higher inductance yields in less ripple current and hence in higher efficiency. the flaw is the slower transient response of the power stage to load transients. this might increase the need for more output capacitors driving the cost up. find a low loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. the core must be large enough not to saturate at the peak inductor current. output capacitor selection output capacitors are used to obtain high bandwidth for the output voltage beyond the bandwidth of the converter itself. usually, the cpu manufacturer recommends a capacitor configuration. two different kinds of output capacitors can be found, bulk capacitors closely located to the inductors and ceramic output capacitors in close proximity to the load. the latter ones are for mid frequency decoupling with especially small esr and esl values while the bulk capacitors have to provide enough stored energy to overcome the low frequency bandwidth gap between the regulator and the cpu. thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance.
RT8856 22 ds8856-03 june 2011 www.richtek.com layout considerations careful pc board layout is critical to achieve low switching losses and clean, stable operation. the switching power stage requires particular attention. if possible, mount all of the power components on the top side of the board with their ground terminals flush against one another. follow these guidelines for optimum pc board layout : ` keep the high current paths short, especially at the ground terminals. ` keep the power traces and load connections short. this is essential for high efficiency. ` connect slew rate control capacitor at soft pin to rgnd. ` when trade offs in trace lengths must be made, it's preferable to allow the inductor charging path to be made longer than the discharging path. ` place the current sense component close to the controller. isenx and isenx_n connections for current limit and voltage positioning must be made using kelvin sense connections to guarantee the current sense accuracy. pcb trace from the sense nodes should be paralleled back to controller. ` route high speed switching nodes away from sensitive analog areas (soft, comp, fb, vsen, isenx, isenx_n, cm, cmset, etc...) figure 10. derating curves for RT8856 packages 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) 1 four layers pcb for recommended operating condition specifications of RT8856, the maximum junction temperature is 125 c and t a is the ambient temperature. the junction to ambient thermal resistance, ja , is layout dependent. for wqfn-40l 6x6 packages, the thermal resistance, ja , is 34 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (34 c/w) = 2.941w for wqfn-40l 6x6 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . for RT8856 package, the derating curve in figure 10 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation.
RT8856 23 ds8856-03 june 2011 www.richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 5.950 6.050 0.234 0.238 d2 4.000 4.750 0.157 0.187 e 5.950 6.050 0.234 0.238 e2 4.000 4.750 0.157 0.187 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 40l qfn 6x6 package d e d2 e2 l b a a1 a3 e 1 see detail a note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2

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